1. Field of the Invention
The present invention generally relates to dynamic random access memory (DRAM) cells. More particularly, the present invention relates to a process for the formation of a thin insulating collar in the capacitive storage trench of DRAM cells.
2. Background and Related Art
Capacitive storage trenches are commonly employed in DRAM cells. A trench capacitor is a three-dimensional structure typically formed in a silicon substrate. A conventional trench capacitor is formed by etching a trench into the substrate. The trench is typically filled with n+ doped polysilicon which serves as one plate of the capacitor (referred to as the storage node). The second plate of the capacitor, referred to as a "buried plate," is formed by, for example, outdiffusing n+ dopants from a dopant source into a region of the substrate surrounding the lower portion of the trench. A dielectric layer is provided to separate the two plates thereby forming the capacitor. To prevent or reduce parasitic leakage that occurs along the upper portion of the trench to an acceptable level, an oxide collar of sufficient thickness is provided therein. Typically, the oxide collar is sufficiently thick to reduce the parasitic leakage to an inappreciable amount. Typical of said prior art trench capacitor DRAM cells is that described in U.S. Pat. No. 5,981,332 to Mandelman, et al., entitled "Reduced Parasitic Leakage In Semiconductor Devices" and assigned to the assignees of the present invention.
It is known that continued demand to shrink devices has facilitated the design of DRAM cells with greater density and smaller feature size and cell area. For example, design rules have been scaled from 0.25 microns (.mu.m) down to about 0.12 nm and below. At the smaller ground rules, the control of vertical parasitic MOSFET leakage from the buried-plate becomes more difficult due to the smaller trench dimensions. This is because a smaller trench opening necessitates a corresponding reduction in collar thickness to facilitate filling of the trench. However, to reduce the parasitic leakage to below an acceptable level, the thickness of the collar needs to be of some minimum dimension, depending on operating voltage conditions. Collar thickness hinders the filling of the smaller trench.
One of the difficulties in fabricating trench collars is that during high temperature process steps used in fabricating the cells, in general, there is a tendency for lateral growth or enlargement of the storage trench shape in the silicon substrate. This is particularly so during the process of thermal oxidation of material used to form the collar itself on the trench wall. Such oxidation steps can cause significant lateral growth of the storage trench due to simultaneous oxidation of the silicon substrate. This is particularly harmful in the fabrication of a hybrid DRAM cells where there is a vertically gated MOSFET within the same storage trench, with a bit line contact positioned above the adjacent vertical gate channel of the MOSFET. In such an arrangement, lateral growth of the trench reduces bit line contact area thereby limiting reduction in cell size or causing device failure.
Another difficulty with fabricating trench collars by means of oxidation of the silicon substrate is the ability to make the collars so they are uniform in thickness throughout the trench circumference without the bumps due to sporadic nucleation; and without thickness variations due to crystallographic effects on the local oxidation rate. Both effects make it difficult to effectively modulate the charge in the collar along the collar-silicon substrate interface. Inability to modulate the charge makes it difficult to control the vertical parasitic leakage and minimize the floating body effect.